In the field of digital logic, extensive use is made of well known and highly developed complimentary metal-oxide semiconductor (CMOS) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions (JJs), with typical signal power of around 4 nanowatts (nW), at a typical data rate of 20 gigabits per second (Gb/s) or greater, and operating temperatures of around 4 kelvins.
A majority gate is a logical gate that returns true if and only if more than 50% of its inputs are true. A flip-flop is a bistable multivibrator, a two-stable-state circuit that can therefore be used to store state information and to change state by signals applied to one or more control inputs. In modern computing and communications electronics, flip-flops are the basic storage element in sequential logic. A conventional D flip-flop, e.g., one implemented in CMOS, has two binary inputs, a data input D and a clock input, and at least one output, Q. The D flip-flop captures the value of the D input at a definite portion of an input clock cycle, e.g., a rising edge or a falling edge, known as the capture time. That captured value becomes the Q output. The output Q does not change except at the capture time (or some small propagation delay thereafter). In practical implementations it is required that a data input D be stable for some setup time prior to the capture time and for some hold time after the capture time for the input to be reliably captured and propagated to the output. “Fan-in” describes the number of inputs a logic gate can handle. The larger the fan-in, the more inputs can be handled by the gate. Logic gates with higher fan-in can be employed in digital logic design to reduce the depth of a logic circuit, improving circuit efficiency and density.
Phase-mode logic allows digital values to be encoded as superconducting phases of one or more JJs. For example, a logical “1” may be encoded as a high phase and a logical “0” may be encoded as a low phase. For example, the phases may be encoded as being zero (meaning, e.g., logical “0”) or 2π (meaning, e.g., logical “1”). These values persist across RQL clock cycles because there is no requirement for a reciprocal pulse to reset the JJ phase.